1. Field of the Invention
The present invention relates to a photolithographic process for manufacturing semiconductor devices. More particularly, the present invention relates to a wafer bearing an alignment mark used to align the wafer with photolithographic exposure equipment, to the manner in such a wafer is produced, to the alignment system which examines the mark to produce the signals used to align the exposure equipment and the wafer, and to the method of aligning the exposure equipment and the wafer.
2. Description of the Related Art
Semiconductor devices typically comprise various circuit patterns stacked on a wafer. The circuit patterns are formed using a photolithographic process. Each circuit pattern formed must be aligned accurately with the circuit pattern which has been formed previously on the wafer. The alignment is achieved by illuminating a predetermined region of the wafer having an alignment mark formed thereon, and using the illuminated region to obtain photoelectric signals indicative of whether the exposure equipment of the photo processing system is properly aligned with the wafer. Typical alignment marks are shown in FIGS. 1 and 2.
The alignment mark shown in FIG. 1 comprises a series of parallel lines. The alignment mark is for use with an off-axis type field image alignment system having a halogen lamp as its source of illumination. The length I of, the width w1 of and the distance s between the lines 10 of the alignment mark are approximately 30 μm, 6 μm and 6 μm, respectively.
The alignment mark shown in FIG. 2 comprises a line 20 having a positive slope with respect to an X-Y coordinate system and a line 25 having a negative slope with respect to the X-Y coordinate system. The height h and the width w2 of the lines 20 and 25 are 82 μm and 1.5 μm, respectively.
Now, the wafer on which the alignment mark has been formed has undergone the various processes for forming previous circuit patterns thereon. These processes affect the integrity of the alignment mark. For instance, a chemical mechanical polishing (CMP) process affects the alignment mark to such an extent that the alignment signals derived therefrom are distorted. CMP is widely used for forming a trench isolation region, planarizing an inter-dielectric layer, forming a plug or forming a damascene interconnection in a semiconductor device to secure a high degree of integration for the device.
FIG. 3 is a sectional view of one of the lines of the alignment marks of FIGS. 1 and 2, as taken along lines III–III′. A layer 5 having a pattern of lines 10 (20) is formed on a wafer 1, and a layer 30 to be subjected to the CMP process is formed on the layer 5. When the structure shown in FIG. 3 undergoes the CMP process, a dishing phenomenon occurs in the layer 30′ which is left by the CMP process, as shown in FIG. 4. This is because the alignment marks are composed of lines which are larger (30×6 μm2) than those making up the line pattern of the semiconductor device, and the line density of the pattern of the alignment mark is very low. The amount of material to be removed by the CMP process is set on the basis of the circuit pattern having a relatively high line density. As the CMP process produces a severe dishing phenomenon in the layer 30′, it is also damaging the pattern of lines 10 (20) of the alignment mark.
The abrasion of the pattern of lines in association with the dishing phenomenon is a root cause of the production of distorted photoelectric signals during the alignment process. Distorted alignment signals in turn limit the degree to which the circuit patterns can be precisely aligned.